Recently, with the increase of packaging density and integration level in semiconductor memory devices, the bit line connected to the memory cell is made thinner and longer. Thus, the wiring resistance tends to increase.
In this context, techniques for backing the bit line with a low resistance metal line have been proposed.
However, simply backing the bit line with a low resistance metal line may fail to reduce the total wiring resistance of the bit line due to problems such as the thin line effect.